FIG. 1 is a block diagram illustrating a conventional digital signal receiving apparatus. In FIG. 1, A/D conversion section 11 performs oversampling on an analog signal at a rate M times the symbol rate to convert into a digital signal. The digital signal is output to FIR filtering section 12. FIR filtering section 12 performs digital filtering on the digital signal output from A/D conversion section 11 to output to phase determining section 13 and decision section 14. Phase determining section 13 determines an optimal phase based on the signal output form FIR filtering section 12, and outputs a determined result to decision section 14. Based on the phase determined in phase determining section 13, decision section 14 makes a decision on the signal output from FIR filtering section 12 to generate bit data.
In the conventional digital signal receiving apparatus, since reception performance deteriorates when a phase determined in phase determining section 13 differs from an optimal phase, general countermeasures are to increase the oversampling number to reduce the deterioration.
FIG. 2 is a graph illustrating the relationship between the oversampling number and reception performance. FIG. 2 shows a simulation result of a case where demodulation is performed by 16 QAM. In FIG. 2, the solid line shows theoretical values, the dotted line shows a case where the oversampling number is 8 times the symbol rate, and the dot-dash line shows a case where the oversampling number is 16 times the symbol rate. As can be seen from FIG. 2, at BER of 10-3, the 8-times oversampling degrades the CN ratio by about 1.5 dB with respect to the theoretical value. Meanwhile, the 16-times oversampling suppresses the degradation to about 0.5 dB with respect to the theoretical value.
However, when the oversampling number is thus increased to prevent the reception performance from deteriorating, the operation speed required for the device becomes extremely fast in processing of signal with a high symbol rate. Therefore, it is necessary to use an A/D converter and digital signal processing device for performing high-speed processing, but such devices need to have high performance, and thus become expensive.
In cope with the foregoing, there is a technique disclosed in Japanese Laid-Open Patent Publication S60-77542. In this technique, filters are arranged in parallel, tap coefficients corresponding to different phases are divided to calculate, and calculated results are multiplexed. According to the technique, it is possible to decrease a required operation speed, but it is necessary to increase the oversampling number or the number of parallel lines of filters to suppress the deterioration of reception performance, corresponding to which, the circuitry scale is increased.
As a technique for reducing the circuitry scale, the invention disclosed in U.S. Pat. No. 1,725,413 is known. The subject matter of the invention is using the symmetry of impulse response train, only storing coefficients corresponding to half an impulse train, and changing the order of reading. However, this technique is limited to a case of calculation using a single product-sum calculator. In other words, since it is required to calculate multiplication with variable coefficients, it is not possible to perform calculation faster than calculation with fixed coefficients.
Further, as another technique for reducing the circuitry scale, the invention disclosed in U.S. Pat. No. 2,100,608 is known. The invention uses input signals not subjected to band limitation, and therefore, is not applicable to a case of performing filtering on received signals with band limitation and thermal noises.
As described above, the conventional techniques do not implement both obtaining fast calculation in FIR filter and reducing the circuitry scale in a digital receiving apparatus.